The duty cycle is an important characteristic of a periodic digital waveform. The duty cycle is generally defined as the ratio of the pulse width (tw) to the period (T) and can be expressed as a percentage.       Duty    ⁢                   ⁢    cycle    =            (                        t          w                T            )        ⁢    100    ⁢    %  
The demand for less expensive, lower power and yet more reliable integrated circuit components for use in communication, imaging and high-quality video applications continues to increase rapidly. Integrated circuit manufacturers are requiring improved performance in the clock signal references for such components and devices to meet the design requirements of such emerging applications. Digital signal processors (“DSPs”) are integral components of these devices. DSPs are one of a variety of devices that require a clock signal with a predetermined duty cycle for proper operation.
To be processed in a DSP system, analog signals must first be converted into digital format. These digital signals are then converted back to an analog signal after being processed by the DSP, for example, for output to a speaker in the case of audible sounds. A coder/decoder device (“Codec”) is often used as a front-end to a DSP. The Codec integrates analog to digital and digital to analog conversion functions on the Codec device. If a device, such as a DSP, requires a clock signal operating at a certain frequency and duty cycle, in many cases the oscillator from the Codec provides such clock signal. For example, it is often desirous to take the generated clock signal and export it from the Codec to the DSP chip.
In order to keep power consumption down, a Codec may only be able to export a clock signal with the desired frequency if it has an irregular duty cycle. This is problematic as DSPs are sensitive to the duty cycle of the clock signal. In the case of DSP, a clock signal with a substantially 50% duty cycle is typically desired. A clock signal with a 50% duty cycle is often described as having a square shape that is high for half of the clock period and low for half of the clock period. The described embodiment of the present invention is able to convert, for example, a clock signal of the desired frequency that has a waveform that is high 67% of the time and low 33% of the time, to a clock signal with the desired frequency that has a waveform that is high 50% of the time and low 50% of the time.
To illustrate, a DSP may require a clock signal with a frequency of 5 MHz and 50% duty cycle. However, the highest frequency clock available to the DSP from a Codec may only be 2.5 MHz. One solution is to increase the clock frequency. However, it is well known in the art that increasing the clock frequency increases the power consumption of a circuit. To overcome this issue, the Codec oscillator that generates the 2.5 MHz clock signal can be adapted to output three (3) different phases of the 2.5 MHz clock signal. Using exclusive-OR techniques, two (2) of the phases can be combined to create the desired 5 MHz clock signal while only minimally increasing the power consumption. However, because the two (2) clock phases are 120° out of phase with respect to one another, the 5 MHz signal may have a duty cycle, that is not high 50% of the time and low 50% of the time, but rather is high 67% of the time and low 33% of the time.
One method for achieving a 50%, or other desired duty cycle, is through the use of phase locked loop (“PLL”) circuits. However, these circuits are complex, requiring many more semiconductor devices, and thus increased chip surface area. Other solutions, such as using comparators, have higher power requirements.
It is an objective of the present invention to provide a clock signal with the desired clock frequency and duty cycle by modifying the clock signal from an oscillator, e.g., from an onboard Codec or similar device having a low operating voltage and a small surface area.